고유전율 절연막/금속 게이트 MOSFET의 신뢰성에 관한 연구
- 고유전율 절연막/금속 게이트 MOSFET의 신뢰성에 관한 연구
- Date Issued
- High-k/metal gate stacks have been successfully implemented in aggressively scaled CMOS devices to increase performance of transistors and to reduce power consumption. Among high-k dielectrics, hafnium-based high-k gate dielectrics have been demonstrated as a strong substitute because of its low Vth, low gate leakage, and good thermal stability in contact with Si. Although many researchers have investigated about the reliability of high-k/metal gate stacks, some critical problems still remain and their physical origins and mechanisms are still unclear. To successfully incorporate the high-k/metal gate stacks into sub 45-nm CMOS technology node, it is necessary to establish assessment theories for critical reliability problems such as bias temperature instability (BTI) and time-dependent dielectric breakdown (TDDB). In this study, the degradation and recovery characteristics of SiGe pMOSFETs with a high-k/metal gate stack under negative-bias temperature instability (NBTI) stress are investigated. The threshold voltage instability (ΔVth) of SiGe pMOSFETs shows an increased percentage of recovery (R) as well as lower degradation than those of control Si pMOSFETs. It is found that the recovery characteristics of SiGe and Si pMOSFETs have similar dependencies on various stress conditions, and the increased R of SiGe pMOSFETs is mainly attributed to their lower degradation characteristic. Under low effective oxide field (Eox) close to real operating conditions, most of the ΔVth caused by bulk traps of high-k would be rapidly recovered through a fast recovery process, and newly-generated interface traps during the stress would determine the degradation level of Vth. The SiGe pMOSFETs show lower stress-induced interface traps
thus, they would display more reliable NBTI characteristics than Si pMOSFETs under real operating conditions. Moreover, the dielectric degradation and breakdown characteristics of HfSiON/SiON gate dielectric nMOSFETs are investigated by using the stress induced leakage current (SILC) analysis. The nMOSFETs show the progressive breakdown (PBD) under substrate injection stress and its characteristic changes as the stress voltage increases, from slow PBD (s-PBD) only, then to a combination of s-PBD and fast PBD (f-PBD), and finally to f-PBD only. It is found that the SILC of nMOSFETs is caused by trap-assisted tunneling mainly through the pre-existing deep traps of the high-k layer and the stress-induced traps of the interfacial layer (IL). The stress-induced defects under substrate injection stress are generated within the IL rather than the high-k layer and the TDDB of the nMOSFETs is driven by the degradation of the IL. Finally, the low-frequency noise characteristics of HfSiON/metal gate stack nMOSFETs with and without La-doping are investigated and new findings on the impact of La-doping on low-frequency noise are reported. It is found that the La-doped devices show lower noise intensity than the control devices and it is attributed to the reduced Nt caused by the La-doping. In the case of submicron devices, however, the La-doped devices show additional mobility-fluctuation noise at low-field condition and the additional noise intensity increases as the gate length decreases. These results indicate that the advantage of low noise of La-doping technique could decrease or even disappear in case of short-channel devices.
- Article Type
- Files in This Item:
- There are no files associated with this item.
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.