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A 110 MHz to 1.4 GHz Locking 40-Phase All-Digital DLL

Title
A 110 MHz to 1.4 GHz Locking 40-Phase All-Digital DLL
Authors
Young-Sang KimSeon-Kyoo LeePark, HJSim, JY
POSTECH Authors
Park, HJSim, JY
Date Issued
Feb-2011
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Abstract
An all-digital DLL is designed to generate low jittery 40 phases in a continuous lock range of 110 MHz to 1.4 GHz. The DLL is driven by dual loops-one for phase lock and the other for offset calibration. The two loops are updated by a chopping PD which adaptively extracts valid information for each loop, one at a time. For the optimal 1-bit delay resolution in the entire lock range, a piecewise profiling of delay line is also proposed. The DLL, fabricated in a 0.13 mu m CMOS, reveals the best linearity performance compared with previously reported works, showing a DNL of less than 0.3 LSB and a INL of less than 0.8 LSB in the entire lock range up to 1.4 GHz. With the piecewise-fitted delay line, the amount of peak-to-peak and rms jitters induced by DLL operation is controlled to be less than 0.825% and 0.2% of the clock period, respectively. Power consumption was 74.4 mW at the supply voltage of 1.2 V.
URI
http://oasis.postech.ac.kr/handle/2014.oak/17571
DOI
10.1109/JSSC.2010.2092996
ISSN
0018-9200
Article Type
Article
Citation
IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 46, no. 2, page. 435 - 444, 2011-02
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 PARK, HONG JUNE
Dept of Electrical Enginrg
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