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저잡음 분수분주형 PLL에 관한 연구

저잡음 분수분주형 PLL에 관한 연구
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This thesis presents several low-noise techniques for the design of fractional-N PLL, including delta-sigma noise filtering techniques and new architectures of time-to-digital converter in digital PLL. First, a FIR-embedded phase interpolator based noise filtering technique is introduced with 1 GHz fractional-N PLL implemented in 0.13 m CMOS. The proposed filtering scheme combines phase rotator based noise filtering and FIR filtering with new architecture of phase interpolator, and demonstrates maximum noise reduction of 34 dB, which is the best noise filtering result up-to-date. Implemented fractional-N PLL achieves the phase noise result of integer-N PLL comparable even with 0.1 x reference frequency loop bandwidth for the first time. Noise shaping ΔΣ TDC with a single delay stage and charge pump based integrator is also introduced as low-noise and low-power dissipation TDC in fractional-N digital PLL. With inherited advantages of high linearity and resolution of delta-sigma modulation, the proposed TDC even filters out the input noise from the delta-sigma modulator based fractional divider. A 2 GHz fractional-N digital PLL is implemented in a 0.13 m CMOS for the verification of proposed TDC, and shows an in-band phase noise of -107 dBc/Hz at 500 kHz offset and an out-of-band phase noise of -118.5 dBc/Hz at 3 MHz offset with TDC power consumption of 1.3 mW. Finally, sub-exponent ΔΣ TDC and IIR-based noise cancelling technique are introduced. The proposed sub-exponent control achieves both the optimum resolution and prevention of stability problem in PLL due to overloading of ΔΣ TDC. IIR filter which emulates the signal transfer function of TDC cancels out the remained DSM at TDC output without tightened matching constraints. The proposed techniques are implemented in a 1.9 GHz fractional-N digital PLL with 0.13 m CMOS process, showing the phase noise of -98 dBc/Hz at 200 kHz offset and -111 dBc/Hz at 3 MHz offset with 500 kHz loop bandwidth while consuming 8.6 mW.
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