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A 1.9-GHz Fractional-N Digital PLL With Subexponent Delta Sigma TDC and IIR-Based Noise Cancellation

Title
A 1.9-GHz Fractional-N Digital PLL With Subexponent Delta Sigma TDC and IIR-Based Noise Cancellation
Authors
Jee, DWKim, BPark, HJSim, JY
POSTECH Authors
Kim, BPark, HJSim, JY
Date Issued
Nov-2012
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Abstract
This brief presents a 1.9-GHz fractional-N digital phase-locked loop (DPLL) with a subexponent Delta Sigma time-to-digital converter (TDC) and an infinite impulse response (IIR)-based noise cancellation scheme. The proposed subexponent Delta Sigma TDC generates adaptively scaled exponent-only information to track the finest resolution that prevents overloading for a given input environment. In addition, IIR-based noise cancellation provides easy filtering of delta-sigma modulator noise without tightened matching constraints. The DPLL fabricated in 0.13-mu m CMOS consumes 8.6 mW and shows the subexponent operation and IIR noise cancellation. The measured phase noise of DPLL is -98 dBc/Hz at 200-kHz offset and -111 dBc/Hz at 3-MHz offset with 500-kHz loop bandwidth.
Keywords
Delta-sigma time-to-digital converter (TDC); digital phase-locked loop (DPLL); fractional-N phase-locked loop (PLL); noise cancellation; subexponent TDC; CONVERTER; TIME
URI
http://oasis.postech.ac.kr/handle/2014.oak/15906
DOI
10.1109/TCSII.2012.2228373
ISSN
1549-7747
Article Type
Article
Citation
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, vol. 59, no. 11, page. 721 - 725, 2012-11
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