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A 1.25 ps Resolution 8b Cyclic TDC in 0.13 mu m CMOS

Title
A 1.25 ps Resolution 8b Cyclic TDC in 0.13 mu m CMOS
Authors
Seo, YHKim, JSPark, HJSim, JY
POSTECH Authors
Park, HJSim, JY
Date Issued
Mar-2012
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Abstract
This paper describes the first implementation of the well-known cyclic ADC architecture into a time-to-digital converter. With an asynchronous clocking scheme, an all-digital 1.5b time-domain multiplying DAC (MDAC) is repetitively used for 8b conversion. The MDAC is based on a 2x time amplifier with an offset-compensated gain calibration scheme. The proposed cyclic TDC, fabricated in a 0.13 mu m CMOS, shows a resolution of 1.25 ps with a total conversion range of +/-160 ps, the maximum operating frequency of 100 MHz, and a power consumption of 4.3 mW at 50 MHz. The measured DNL and INL are +/-0.7 LSB and -3 to +1 LSB, respectively.
Keywords
All-digital PLL; time amplifier; time-to-digital converter; TO-DIGITAL CONVERTER
URI
http://oasis.postech.ac.kr/handle/2014.oak/15904
DOI
10.1109/JSSC.2011.2176609
ISSN
0018-9200
Article Type
Article
Citation
IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 47, no. 3, page. 736 - 743, 2012-03
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 PARK, HONG JUNE
Dept of Electrical Enginrg
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