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A Single-Loop SS-LMS Algorithm With Single-Ended Integrating DFE Receiver for Multi-Drop DRAM Interface

Title
A Single-Loop SS-LMS Algorithm With Single-Ended Integrating DFE Receiver for Multi-Drop DRAM Interface
Authors
Chi, HJLee, JSJeon, SHBae, SJSohn, YSSim, JYPark, HJ박홍준
Date Issued
Sep-2011
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Abstract
A 3.8 Gb/s multi-drop single-ended integrating DFE (IDFE) receiver is implemented in a 0.18 um CMOS by using a single-loop LMS-algorithm to find the DFE coefficients automatically. Initially, a preamble input data pattern ('1101') is applied to the main IDFE circuit to determine the DFE coefficients, while a fixed input data pattern ('1111') is applied to the replica IDFE circuit. The difference between the outputs of the two IDFE circuits is used in the feedback loop to determine the DFE coefficients. The reference voltage (Vref) of preamplifier is generated inside chip by a Vref loop to reduce the effect of the external noise and the input offset voltage of preamplifier and IDFE circuits and also to track the mid-level of the input data swing in spite of process variations of TX chips. An integrating deskew scheme with a minimum overhead is introduced. 2-drop and 4-drop DRAM channels are tested. The maximum data rate was increased from 1.0 Gb/s to 2.6 Gb/s by DFE in the heavily loaded 4-drop interface, from 3.5 Gb/s to 3.8 Gb/s by DFE in the 2-drop interface.
Keywords
Decision feedback equalization; DFE; DRAM interface; equalizer; integration; ISI; multi-drop bus; single-ended signaling; SS-LMS; DECISION-FEEDBACK EQUALIZATION; SERIAL LINK; CMOS; COMPENSATION; PREEMPHASIS; TRANSCEIVER; SCHEME
URI
http://oasis.postech.ac.kr/handle/2014.oak/15815
DOI
10.1109/JSSC.2011.2136590
ISSN
0018-9200
Article Type
ARTICLE
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