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A Memory-Mapped Invert Coding Scheme for Phase-Change Memory

Title
A Memory-Mapped Invert Coding Scheme for Phase-Change Memory
Authors
Alain TRAN
Date Issued
2012
Publisher
포항공과대학교
Abstract
Phase-change memory (PRAM) is expected to become a part of main memory subsystems as PRAM compensates for several weaknesses of DRAM such as standby power and scaling. However, PRAM suffers from major limitations related to write operations. Among them, PRAM’s poor write endurance can limit the device lifetime. This paper proposes a new Memory-Mapped Invert-Coding scheme to reduce the total of number of bit updates by applying invert code (IC) at a hybrid granularity with fine-grain IC mapped onto PRAM address space. We propose a DRAM/DRAM memory controller design to incorporate our solution and in which frequently accessed fine-grain IC is cached in DRAM. We provide an application-specific design-time solution that takes into account the bit updates reduction capability per memory region. Experimental results show that our methods achieves 9.4% more reduction in total bit updates over the baseline for only 1% additional PRAM area overhead.
URI
http://postech.dcollection.net/jsp/common/DcLoOrgPer.jsp?sItemId=000001219518
http://oasis.postech.ac.kr/handle/2014.oak/1506
Article Type
Thesis
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