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Reassessment of Dynamic Stress Degradation for Nanoscale MOSFETs Operating in a CMOS Inverter at High Temperature

Reassessment of Dynamic Stress Degradation for Nanoscale MOSFETs Operating in a CMOS Inverter at High Temperature
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This thesis investigates the effect of dynamic stress (ON/OFF waveform) on reliability of nanoscale n-and p- channel MOSFETs operating in a CMOS inverter at high temperature. New experimental findings and their underlying degradation mechanisms were described in detail. For nanoscale nMOSFETs with SiON gate dielectric, the OFF-state degradation by drain-induced barrier lowering (DIBL) was observed at high temperature. Experimental results indicate that acceptor-like interface traps Nit, positive oxide charges Qox, and neutral electron traps were generated by the OFF-state stress. Although the subsequent ON-state did not produce any new defects, it filled the neutral electron traps and neutralized positive Qox’s, which increased threshold voltage Vth and decreased the OFF-current significantly. A consecutive application of OFF and ON-states caused a buildup of recoverable and permanent electron traps, and interface traps, thus resulting in the significant increase in Vth. The dynamic stress degradation was frequency f-independent up to 500 kHz, which confirms that the transition between ON and OFF-states did not influence the Vth. This implies that the OFF-state-induced defects were the main cause for dynamic stress degradation, which caused a decrease in lifetime of nanoscale nMOSFETs. For nanoscale p¬MOSFETs with SiON gate dielectric, OFF-state degradation by DIBL was also observed at high temperature. Experimental results indicate that the OFF-state stress generated donor-like Nit’s and negative Qox’s, localized near the drain. The ON-state stress produced the negative bias temperature instability (NBTI) which generated Nit’s and positive Qox’s distributed uniformly in the channel. Although the electrons trapped by the OFF-state stress decreased Vth, they were de-trapped readily by the subsequent ON-state stress. Therefore, a consecutive application of OFF and ON-states caused the nanoscale pMOSFET to buildup Nit and positive Qox, which increased Vthsignificantly. Unlike the nMOSFETs, the dynamic stress degradation of pMOSFETs was strongly dependent on the f. When the f was increased, the ON-state (NBTI) degradation was reduced significantly. In contrast, the OFF-state stress suppressed the decrease in Vth with an increase in f because the hot electrons could not be trapped in the oxide located far from the Si interface. These experimental results suggest that the dynamic stress degradation at low f is attributed to both the NBTI- and OFF-state-induced defects while that at high f is influenced by the OFF-state-induced defects only. Dynamic stress degradation of pMOSFETs with TiN/HfSiO gate stacks was also investigated. A consecutive application of dynamic stresses casues a buildup of Nit and electron traps during OFF-state period, and NBTI-induced defects during ON-state period, similar to SiON devices. Unlike SiON devices, however, the OFF-state induced defects did not influence Vth during the subsequent ON-state while the ON-state induced defects were recovered significantly due to the electron trapping during the subsequent OFF-state, thus leading to a more amount of NBTI recovery at an ON/OFF waveform than that at a typical gate-pulsed NBTI (OFF-state at gate bias Vg = drain bias Vd = 0 V). This result indicates that the OFF-state stress can improve the lifetime of pMOSFETs with high-k dielectrics in a scaled circuit. The new experimental observations in this thesis suggest that the OFF-state degradation by the DIBL can impose a significant limitation on CMOS device scaling, thus requiring methods of reducing the DIBL effect while keeping the other device characteristics remaining.
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