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A 10-bit 25-MS/s 1.25-mW Pipelined ADC With a Semidigital Gm-Based Amplifier

Title
A 10-bit 25-MS/s 1.25-mW Pipelined ADC With a Semidigital Gm-Based Amplifier
Authors
Yunjae SuhLee, JongmiKim, ByungsubPark, HJSim, JY
POSTECH Authors
Park, HJSim, JY
Date Issued
Mar-2013
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Abstract
A semidigital Gm-based amplifier is proposed for a low-power pipelined analog-to-digital converter (ADC). The amplifier performs a class-AB operation by smoothly changing between a comparator-like semidigital driver and a continuous-time high-gain amplifier according to the input voltage difference. A 10-bit pipelined ADC with 2.5-bit/stage architecture is implemented in a 0.13-mu m CMOS. The ADC consumes 1.25 mW at a sampling rate of 25 MS/s and achieves a Nyquist-rate figure-of-merit of 139 and 232 fJ/c-s without and with power consumption from a resistor ladder, respectively.
Keywords
Analog-to-digital converter (ADC); Gm-based amplifier; operational transconductance amplifier (OTA); pipelined ADC; semidigital amplifier; 50 MS/S; OP-AMP; DESIGN; OPAMP
URI
http://oasis.postech.ac.kr/handle/2014.oak/14578
DOI
10.1109/TCSII.2013.2240832
ISSN
1549-7747
Article Type
Article
Citation
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, vol. 60, no. 3, page. 142 - 146, 2013-03
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 PARK, HONG JUNE
Dept of Electrical Enginrg
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