Open Access System for Information Sharing

Login Library

 

Article
Cited 3 time in webofscience Cited 4 time in scopus
Metadata Downloads

A QDR-Based 6-GB/s Parallel Transceiver With Current-Regulated Voltage-Mode Output Driver and Byte CDR for Memory Interface

Title
A QDR-Based 6-GB/s Parallel Transceiver With Current-Regulated Voltage-Mode Output Driver and Byte CDR for Memory Interface
Authors
Seon-Kyoo LeeKim, BPark, HJSim, JY
POSTECH Authors
Kim, BPark, HJSim, JY
Date Issued
Feb-2013
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Abstract
This brief presents an 8-bit parallel transceiver for low-power memory interface with a current-regulated voltage-mode driver and a clock and data recovery performing both bit recovery and byte alignment. Sharing a current source by output drivers enables voltage swing control without any regulator circuit while holding the benefits of low-power voltage-mode driving. In the receiver, with only one phase rotator in a globally shared phase-locked loop, a narrow-range delay line in each deskewing phase recovery loop effectively performs seamless phase adjustment. The transceiver, implemented in a 90-nm CMOS, shows a data rate of 6 Gbit/s/ch with a bit error rate of 10(-12) and a power consumption of 2.8 mW/Gbit/s.
Keywords
Clock and data recoveries (CDRs); low-power links; memory interface; parallel links; CMOS
URI
http://oasis.postech.ac.kr/handle/2014.oak/14577
DOI
10.1109/TCSII.2012.2234992
ISSN
1549-7747
Article Type
Article
Citation
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, vol. 60, no. 2, page. 91 - 95, 2013-02
Files in This Item:
There are no files associated with this item.

qr_code

  • mendeley

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.

Related Researcher

Researcher

 KIM, BYUNGSUB
Dept of Electrical Enginrg
Read more

Views & Downloads

Browse