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Cited 6 time in webofscience Cited 8 time in scopus
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A 0.5-V, 1.47-mu W 40-kS/s 13-bit SAR ADC With Capacitor Error Compensation

Title
A 0.5-V, 1.47-mu W 40-kS/s 13-bit SAR ADC With Capacitor Error Compensation
Authors
Ha, HLee, SKKim, BPark, HJSim, JY
POSTECH Authors
Kim, BPark, HJSim, JY
Date Issued
Nov-2014
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Abstract
A 13-bit successive approximation analog-to-digital converter (ADC) is presented for an ultralow-power sensor interface. Capacitor error compensation is achieved by swapping the roles of two identical capacitor banks in a digital-to-analog converter. The ADC is implemented in a standard 0.13-mu m CMOS. With a single supply voltage of 0.5 V and a rail-to-rail conversion range, the ADC dissipates 1.47 mu W at a sampling rate of 40 kS/s. It shows a figure of merit of 17.9 fJ/conversion-step with an effective number of 11.0 bits.
Keywords
Capacitor mismatch compensation; high resolution; sensor interface; successive approximation register (SAR); analog-to-digital converter (ADC); ultralow power
URI
http://oasis.postech.ac.kr/handle/2014.oak/13817
DOI
10.1109/TCSII.2014.2350378
ISSN
1549-7747
Article Type
Article
Citation
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, vol. 61, no. 11, page. 840 - 844, 2014-11
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 KIM, BYUNGSUB
Dept of Electrical Enginrg
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