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Performance Enhancement of Doherty Power Amplifiers Using Digital Predistortion and Driving Amplifier

Title
Performance Enhancement of Doherty Power Amplifiers Using Digital Predistortion and Driving Amplifier
Authors
이문우
Date Issued
2012
Publisher
포항공과대학교
Abstract
This dissertation is about the enhancement of the efficiency and linearity of Doherty power amplifies (DPAs). The DPA has been regarded as the promising solution to achieve high efficiency. However, The DPAs have limitations to improve both the efficiency and linearity simultaneously. Thus, we have proposed the memoryless digital predistortion (DPD) with optimum bias conditions, split augmented Hammerstein model using the neural network, DPAs with a flat gain, three-stage GaN HEMT DPA with an adaptive driving amplifier, inverted three-stage DPA, and a dual-mode DPA in this thesis. The optimum bias to achieve a highly efficient and linear DPA with memoryless DPD has been investigated. The DPA is implemented using 25-W GaN HEMTs. Power-added efficiency (PAE) of 54.5% is achieved at an output power of 40 dBm for a 2.14-GHz continuous wave. The bias optimization and memoryless DPD are employed to improve the linearity of the DPA. For a one-carrier WCDMA signal at an output power of 36 dBm, the adjacent channel leakage ratio (ACLR) at ±5-MHz offset are below -48 dBc with the drain efficiency (DE) of 40% after the linearization with the optimum bias. The split augmented Hammerstein (SAH) model with an additional distortion path is proposed. The error signal between the source signal and the output signal of the augmented Hammerstein (AH) model is employed to enhance the accuracy of the AH model. To validate the performance of the SAH model, a 2-FA wideband code division multiple access (WCDMA) signal with 10-MHz carrier spacing at 2.14 GHz is employed. The validation results demonstrate that the SAH model can characterize the memory effects as well as the nonlinearity more accurately than the AH model. Furthermore, the SAH model with a neural network (NN) for the three-stage DPA has been described. The NN in the memoryless system is used to characterize the severe nonlinear changes in the magnitude and phase distortions. The three-stage DPA implemented by Si LDMOSFETs is used to validate the performance of the proposed model. For a 2-FA WCDMA signal with 10-MHz carrier spacing, the experimental results show that the proposed model characterizes not only the inconsistent changes in the static nonlinearity, but also the memory effects of the three-stage DPA. DPAs with cascaded peaking cells have been suggested to have high gain and efficiency. The auxiliary peaking cell at the input of the main peaking cell is employed to enhance the efficiency and linearity of DPAs. For the experimental validation, a main DPA and an auxiliary peaking cell are designed using Si LDMOSFETs and a GaN HEMT, respectively. From the measured results, the PAE is increased at a 6-dB back-off power and the ACLR is enhanced over a whole output power range. Moreover, a three-stage DPA with a flat gain have been implemented. For a continuous wave signal, PAEs of 34.0 % and 39.3 % are obtained at 8.5-dB back-off power (BOP) and 4.0-dB BOP from the saturation output power, respectively. The measured one-carrier wideband code division multiple access results show high efficiency and flat gain characteristics over the entire output power range. New three-stage DPAs with an adaptive driving amplifier have been proposed. The driving amplifier inserted at the input of the carrier cell controls the input power of the carrier cell to eliminate the gate leakage current at high input power levels. The gate bias voltage of the driving amplifier is adjusted using an envelope tracking technique according to input power levels. For verifications, the driving amplifier, carrier, and peaking cells are fabricated using 10-W, 15-W, and 35-W GaN HEMTs, respectively, at 3.5 GHz. From a continuous wave, the total DEs of 37.3% and 45.6% are achieved at approximately 9.5- and 4.3-dB BOPs, respectively. For a WiMAX signal, the proposed DPA has the total DE of 39.5 % at an 8-dB BOP. We have analyzed the three-stage inverted DPA using 30-W and 50-W Si LDMOSFETs. The characteristic impedances of the output combiner are derived to achieve high efficiency at a large BOP. The output matching networks and offset lines of the carrier and peaking cells are used to modulate the load impedance. The transmission line in the input path of the carrier cell is inserted to adjust the delay among the carrier and peaking cells. The DE of 40.3 % with a gain of 9 dB is achieved at output power of 42 dBm (8.5-dB BOP) and the DE above 40 % is maintained in wide output power range for a 2.14 GHz continuous wave signal. For a one-carrier WCDMA signal at an output power of 40 dBm (10.5-dB BOP), the DE of 35 % with the gain of 9.2 dB is achieved. The dual-band inverse class-E DPA has been represented. The inverse class-E PAs with double composite right/left handed transmission lines are used as the carrier and peaking cells. Dual-band transformers are employed for the load modulation and the impedance transformer. The dual-band power divider equally divides the input power at two operating frequencies. For verification, the carrier and peaking cells are fabricated using 25-W GaN HEMTs at 900 MHz and 2.14 GHz. The measured results show that DE of 53.5% and 52.7% are achieved at 6-dB back-off powers for 900 MHz and 2.14 GHz continuous waves, respectively.
URI
http://postech.dcollection.net/jsp/common/DcLoOrgPer.jsp?sItemId=000001215275
http://oasis.postech.ac.kr/handle/2014.oak/1316
Article Type
Thesis
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