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Physical Analysis of the Electrical Characteristics in Double-Gate Field Effect Transistors with Gate-Source/Drain Underlap

Physical Analysis of the Electrical Characteristics in Double-Gate Field Effect Transistors with Gate-Source/Drain Underlap
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I present numerical simulation results and physical analysis of the electrical characteristics in Double-Gate Field Effect Transistors (DG FETs) with Gate-Source/Drain Underlap. For the reasonable simulation results, I decided the models and specifications of target devices as followed the previous studies and ITRS. Moreover, I limited the range of lateral abruptness (delta S/D) and included SALICIDE structure for more realistic results. On this basis, I did in-depth studies about underlap papers and verified the results with my device specifications. From these results, I found the short channel effect (SCE) reduction by the drain induced barrier lowering (DIBL) analysis and leakage current reduction by the gate-induced drain leakage (GIDL) enhancement
DIBL is ~ 40% and GIDL is ~ 30% reduced by 3 nm underlap. Moreover, I found the gate leakage current reduction and reliability enhancement in underlap and explored its mechanism from solo-underlap method. I found that the drain solo-underlap is more recommendable than source side underlap from the solo-underlap research, also. Additionally, the fringe-induced barrier lowering (FIBL) effect in high-k device is verified and it is shown that the disadvantages can be recovered from when over 2.5 nm underlap is adjusted. Finally, the capacitance reduction and intrinsic delay enhancement in my underlap devices are verified
intrinsic delay is ~ 30% reduced at 4 nm underlap comparing with 1 nm underlap device. Next, simplified models of capacitance, resistance and carrier mobility are presented and analyzed for DG FinFETs with self-aligned silicide structure in viewing of ??S/D engineering and underlap length (Lun) engineering. The accuracy was vefied from the error check than the maximum error was under 3 % and universality of these models was confirmed using a 2-D device simulator in ITRS projections for high-performance (HP) and low standby power technology (LSPT). My models predict that the adjustment of gate-source/drain underlap in nano scale DG FETs can reduce not only the leakage current but the intrinsic delay by the outer fringe capacitance reduction, external region mobility enhancement, and adjusting the ‥sigma factor… in resistance calculation. In my specification, the reduction ratioes of both leakage current and intrinsic delay are about 30 %. Finally, I present how a single dopant in the channel region effects the variation of threshold voltage delta Vth in highly scaled and undoped DG FETs as the new application of underlap work-area. The presence of a single contaminant dopant in an undoped channel region with an abrupt source/drain (S/D) doping gradient can cause a severe change in Vth (140 mV owing to a single acceptor
100 mV owing to a single donor). To effectively suppress this severe variation, I suggest S/D doping gradient engineering to make sigma S/D larger than 2 nm to minimize delta Vth. The distribution of Vth is also estimated by three-dimensional simulation using the position of the dopant.
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