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A Study on the Impact of Device Parameters on Electrical Characteristics and Optimal Design in Tri-Gate MOSFETs

A Study on the Impact of Device Parameters on Electrical Characteristics and Optimal Design in Tri-Gate MOSFETs
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The development of silicon planar technology over the past half-century has been one of the most important achievements in modern engineering history. With the fundamental physical limits approaching rapidly in CMOS scaling, reducing the device size is especially difficult. New structures must be developed to overcome this challenge. Among the various device structures, the multiple-gate FinFET is emerging as a strong candidate due to better control of short-channel effects (SCEs), ideal subthreshold slope, lower leakage current level, and process compatibility with conventional CMOS technology. Multiple-gate FinFETs have been implemented on silicon-on-insulator (SOI) or bulk Si wafers due to their different merits and applications. SOI FinFETs have been developed mainly for high-speed and high-performance applications because of their low parasitic capacitance and high current drivability, but they have disadvantages in terms of their wafer cost, defect density, floating body effects, and heat-accumulation issues. Thus, body-tied FinFETs, which can overcome these problems while keeping the excellent scalability and performance of SOI FinFETs, are increasingly being investigated. In this dissertation, the impact of device parameters on the electrical characteristics and optimal design in tri-gate MOSFETs was investigated through 3-dimensional device simulations. The total dose response was investigated for various fin widths and bias conditions. First, one of the intuitive objections to the gate-wrap-around design of the FinFETs is the possible negative impact of the corner effect. The behavior of tri-gate MOSFETs has been shown to be significantly influenced by the increased carrier density at the corner regions of a heavily doped channel. There is early conduction at the top corner transistor in tri-gate MOSFETs that controls the threshold voltage by the body doping concentration. The influence of the fin height, radius of curvature, gate length, gate oxide thickness, and dielectric constant of the gate insulator on the device’s electrical characteristics was investigated. The threshold voltages of corner and main regions were easily extracted using the transconductance change method. The phenomenon of channel separation is present only if high doping concentrations and corners with no radius of curvature are used in long-channel devices. For channel doping concentrations higher than 5 × 1018 cm-3, the corner transistor turns on earlier than the main transistor. This is significantly reduced with rounded corners, thin gate oxides, and high-k gate dielectrics. However, earlier conduction of corner regions is not effectively suppressed in tri-gate body-tied MOSFETs although corner regions are rounded with a large radius of curvature. Secondly, as sub-50 nm gate length MOSFETs have undoped ultrathin silicon film for enhanced channel mobility, a possible option to control SCEs and achieve low off-current is to engineer source/drain extension (SDE) regions by optimizing spacer length (Lsp) and lateral source/drain doping gradient (Ldg) instead of the conventional method of increasing the channel doping and/or changing the height/thickness of the silicon film. SDE region engineering is also important to analyze because an intrinsic channel not only avoids random dopant fluctuations and offers higher carrier mobility but also indicates the possibility of a source/drain punch through when SDE regions are heavily doped, thus minimizing the extension region resistance to achieve higher on-current. The influence of source/drain extension region engineering and high-k gate dielectrics on device performance of tri-gate body-tied MOSFETs was investigated to achieve the ITRS projections for HP logic technology. The impact of lateral source/drain doping gradient, spacer length, and spacer length to lateral doping gradient ratio on SCEs is extensively analyzed using three-dimensional device simulations. A lateral doping gradient along with the appropriate spacer length not only can effectively control SCEs, resulting in a low off-current, but can also be optimized to achieve low values of intrinsic gate delay and high values of on-current. A spacer length to lateral doping gradient ratio between 2.7 and 4 is optimal for achieving low intrinsic gate delay, a low off-current and a high on/off-current ratio. The present work provides valuable design guidelines in the performance of tri-gate body-tied MOSFETs with optimal source/drain engineering and serves as a tool to optimize important device and technological parameters. Thirdly, omega-shaped MOSFETs are advanced tri-gate MOSFETs, where the omega-shaped gate wraps around most of the silicon film. This particular device structure provides enhanced electrostatic control of the fin and of the buried oxide (BOX), owing to the additional lateral gates. The electrostatic control is sufficient to screen the radiation-induced charges in the BOX that usually degrade the electrical characteristics of transistors. The lateral coupling becomes dominant, leading to more complex three-dimensional effects. These effects are geometry dependent, varying with the fin width. It was demonstrated that ON-state irradiation is the worst-case bias configuration for tri-gate MOSFETs through extensive experimental analysis. The total dose response was investigated for various fin widths and bias conditions. The higher total-dose tolerance of tri-gate MOSFETs with narrow fins is attributed to lateral gate control over the electrostatic potential throughout the Si film and essentially at the Si fin/BOX interface. The narrow fin devices reduce the influence of the radiation-induced charges in the BOX on the device characteristics. The mechanism is verified by irradiation with various bias conditions and three-dimensional device simulations.
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