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A 5Gb/s Transmitter with a Self-Calibration of Pre-Emphasis Strength and High-Resolution TDCs for ADPLL

Title
A 5Gb/s Transmitter with a Self-Calibration of Pre-Emphasis Strength and High-Resolution TDCs for ADPLL
Authors
서영훈
Date Issued
2011
Publisher
포항공과대학교
Abstract
In this thesis, a 5 Gb/s Transmitter with a TDR-Based Self-Calibration of Pre-Emphasis Strength, a 1GHz Digital PLL with a 3ps-Resolution Floating-Point Number TDC, and a 2 GHz all-digital fractional-N PLL with a 0.63ps-Resolution, 11b Pipeline TDC are proposed. Firstly, a differentially terminated CML transmitter with a self-calibration scheme based on time-domain reflectometry for the pre-emphasis strength control is presented. Without any handshaking or receiver mode control, the transmitter measures the time-of-flight by applying the same step input on the two transmission lines of differential link. Since the receiver does not change its configuration, the proposed scheme greatly simplifies the pre-emphasis adaptation. To verify the calibration scheme, the proposed transmitter is fabricated in a 0.18 ??m CMOS. For various lengths of the microstrip line on PCB up to 80 cm, the tested transmitter greatly improves signal integrity and shows clear eye diagrams at 5 Gb/s. Secondly, a new concept of floating-point number representation is implemented in a time-to-digital converter (TDC) which adaptively scales its resolution according to the amount of input difference. With a fixed 6-bit significand number, the TDC provides 5 cases of the exponent (x1, x2, x4, x8, and x16) to indicate the scale information. A digital PLL with the TDC is implemented in a 0.18 ??m CMOS. The TDC shows the minimum resolution of 3 ps with a total conversion range of 3.5ns, the maximum operating frequency of 80MHz, and power consumption of 18mW at 75MHz. The PLL shows a lock range of 0.9-to-1.25GHz and a rms jitter of 3.5 ps at 1.2 GHz. Finally, a 11b pipeline TDC based on time-domain 1.5b MDAC stages is implemented in a 0.13??m CMOS. The TDC achieves the finest 1b resolution of 0.63ps ever reported in a conversion range of 1.3ns, DNL of ?b0.5LSB, and INL of ?b2LSB. When used in a 2 GHz all-digital fractional-N PLL, measured phase noise is -109 dBc at 1 MHz offset.
URI
http://postech.dcollection.net/jsp/common/DcLoOrgPer.jsp?sItemId=000000900622
http://oasis.postech.ac.kr/handle/2014.oak/1099
Article Type
Thesis
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