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FPGA Implementation of USB 2.0 Serail Interface Engine Chip Using Verilog

Title
FPGA Implementation of USB 2.0 Serail Interface Engine Chip Using Verilog
Authors
성기환
Date Issued
2011
Publisher
포항공과대학교
Abstract
This research implements USB 2.0 Serial Interface Engine (SIE) using Verilog. The implemented SIE consists of packet disassembly, protocol engine and packet assembly. The implemented SIE verifies the correct operation using input pattern of IN/OUT Transaction, thereby checking Token, Data, Handshake packet identification, Data packet Generation, Handshake packet Generation, CRC checking and Generation. The SIE is implemented on Xilinx Virtex-5 FPGA chip and uses 8775 gates. To behavioral simulate, NC-verilog simulator is used. To synthesis and post simulate, ISE software program is used.
URI
http://postech.dcollection.net/jsp/common/DcLoOrgPer.jsp?sItemId=000000900598
http://oasis.postech.ac.kr/handle/2014.oak/1097
Article Type
Thesis
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