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Gate-All-Around Si-Nanowire FETs의 전기적 특성 평가 및 모델링

Gate-All-Around Si-Nanowire FETs의 전기적 특성 평가 및 모델링
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Recently, the conventional planar MOSFET is caught on the barrier scaling to sub 22 nm technology node. Non-classical CMOS technology is expected to provide a path to overcome this limitation using the new materials and new transistor structural designs. The Gate-All-Around Si-Nanowire FET (Si-NWFET) is the one of the most desired candidate to bring sub 22 nm technology into viable production stage throughout the excellent gate controllability and the silicon process compatibility. However, the electrical characteristics of Si-NWFET are not yet sufficiently investigated. In this thesis, the C-V data are presented, measured from nanowire capacitors (NWCAP), which have been fabricated by connecting in parallel a large number of identically processed nanowire FETs. The C-V curves were examined over a range from accumulation to inversion with varying frequencies and at different electrode configurations. The gate response of undoped and floating channel is investigated using C-V data and the inversion charge and carrier mobility are accurately extracted by eliminating the effects of parasitic capacitances and series resistance Rsd. These observed data are compared with data from planar MOS capacitor (MOSCAP). Moreover, the series resistance, Rsd in Si-NWFET is extracted unambiguously, using the Y-function technique, in conjunction with the drain current and transconductance data. The volume channel inversion in Si-NWFET renders the charge carriers relatively free of the surface scattering and concomitant degradation of mobility. As a result, the Y-function of Si-NWFET is shown to exhibit a linear behavior in strong inversion, thereby enabling accurate extraction of Rsd. The technique is applied to nanowire devices with channel lengths 82, 86, 96, 106, 132, and 164 nm, respectively. The extracted Rsd values are shown nearly flat with respect to the gate voltage, as expected from Ohmic contacts but showed a large variation for all channel lengths examined. This indicates the process parameters involved in the formation of series contacts vary considerably from device to device. The present method only requires a single device for extraction of Rsd and the iteration procedure for data fitting is fast and stable. By using the Rsd extraction technique, the series resistance Rsd and the electron and hole mobilities, extracted from n- and p-type Si-NWFETs are compared. Both n- and p-NWFETs show similar Rsd values but n-NWFETs have larger Rsd variation from device to device than p-NWFETs. Also, compared with n-NWFETs, p-NWFETs exhibit higher low-field mobility ??0 but severe mobility degradation, regardless of channel length in the high gate voltage Vgs region. With decreasing channel length and increasing lateral electric field for a given drain voltage, n-NWFETs exhibit low-field mobility (??0) degradation resulting from the velocity saturation. In contrast, the hole mobility in p-NWFETs remains nearly constant and is consistent with its larger critical electric field, Ec. Finally, the volume trap densities Nt are extracted from gate-all-around Si-NWFETs with different gate oxides, using a cylindrical-coordinate-based flicker noise model developed. For extracting Nt, the drain-current power spectral densities were measured from a large number of identical devices and averaged over, thereby mimicking the spatial distribution of trap sites inducing 1/f curve. Also, effective mobility and threshold voltage were simultaneously extracted with the series resistance to characterize the 1/f noise in terms of intrinsic values of these two channel parameters. The volume trap densities thus extracted from different oxides (in situ steam-generated oxide/rapid thermal oxide/nitride-gated oxide) are compared and further examined using hot-carrier stress data. Furthermore, radius dependence of the cylindrical 1/f model developed is discussed.
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