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Transmitter Circuits to Compensate for the Crosstalk-induced Jitter by Controlling the Timing or Transition Waveform of Data Signal in Parallel Microstrip Lines

Title
Transmitter Circuits to Compensate for the Crosstalk-induced Jitter by Controlling the Timing or Transition Waveform of Data Signal in Parallel Microstrip Lines
Authors
정해강
Date Issued
2011
Publisher
포항공과대학교
Abstract
In this thesis, transmitter circuits to compensate for the Crosstalk-induced jitter (CIJ) in parallel microstrip lines on printed circuit board (PCB) are proposed. Two transmitters in chapter 2 and 3 compensate for the CIJ by controlling the timing of data signal. Two transmitters in chapter 4 and 5 compensate for the CIJ by controlling the transition waveform of data signal. Chapter 1 briefly introduces the motivation and organization of this thesis. In chapter 2, the proposed transmitter compensates for the CIJ by using the data timing control at transmitter (TX) in the 3-bit parallel data transmission through the coupled microstrip lines. The difference in propagation velocity with the signal modes (odd, static, even) is compensated for by sending data earlier or later at TX according to the signal modes, so that the signals of different modes arrive at receiver at the same time. The proposed TX was implemented by using a 0.18 μm CMOS process. The measurement shows that the proposed TX reduces the RX jitters by about 30 ps (more than 50% of the added jitter due to CIJ and ISI) at the data rates from 2.6 Gbps to 4.0 Gbps. The proposed scheme can be applied to more than three parallel microstrip lines. In chapter 3, the proposed transmitter compensates for the CIJ by using the clock timing control at transmitter (TX) in the 2-bit parallel data transmission through the coupled microstrip lines. Compared to the authors’ prior work in chapter 2, the delay block circuit is simplified by combining a delay block with a minimal number of stages and a 3-to-1 multiplexer. The delay block generates three clock signals with different delays corresponding to the channel delay of three different signal modes. The 3-to-1 multiplexer selects one of the three clock signals for TX timing depending on the signal mode. The TX is implemented by using a 0.18 μm CMOS process. The measurement shows that the TX reduces the RX jitters by about 38 ps at the data rates from 2.6 Gbps to 3.8 Gbps. Compared to the authors’ prior work in chapter 2, the amount of RX Jitter reduction increases from 28 ps to 38 ps by using the improved implementation. In chapter 4, a single-ended transmitter eliminates the crosstalk-induced jitter at receiver by controlling the slew rates of the signal at transmitter for the even and odd modes of two parallel coupled microstrip lines. The transmitter chip in a 0.18 μm CMOS process reduces the total RX jitter by about 38 ps (53%) for the data rates from 2.6 to 5 Gbps, and increases the horizontal eye-opening (BER < 1E-12) by about 21% at 5 Gbps. In chapter 5, a single-ended transmitter (TX) is proposed to compensate for the crosstalk-induced jitter (CIJ) of coupled microstrip lines by superimposing a rectangular waveform to a data signal at TX during the data transition time, depending on the data transition of an adjacent line. Since the CIJ is proportional to the time derivative of data signal, thus rectangular waveform added at TX cancels the CIJ at RX for the linearly changing data signal with time. As a by-product, this scheme reduces ISI as well as CIJ at RX. The TX chip in a 0.13 μm CMOS improved the time and voltage openings (BER< 1E-12) by 0.32 UI and 80 mV, respectively, in the measured shmoo plot at 6 Gbps.
URI
http://postech.dcollection.net/jsp/common/DcLoOrgPer.jsp?sItemId=000000897307
http://oasis.postech.ac.kr/handle/2014.oak/1011
Article Type
Thesis
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