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dc.contributor.authorBAEK, ROCK HYUN-
dc.contributor.authorYOON, JUN SIK-
dc.contributor.authorJINSU, JEONG-
dc.contributor.authorSEUNGHWAN, LEE-
dc.contributor.authorCHOI, HYUNCHUL-
dc.date.available2020-01-06T04:50:14Z-
dc.date.created2020-01-06-
dc.date.issued2020-03-17-
dc.identifier.urihttp://oasis.postech.ac.kr/handle/2014.oak/100681-
dc.publisherIEEE-
dc.relation.ispartof4th IEEE Electron Devices Technology and Manufacturing (EDTM) Conference 2020-
dc.titleNeural Network Based Design Optimization of 14-nm Node Fully-Depleted SOI FET for SoC and 3DIC applications-
dc.typeConference-
dc.type.rimsCONF-
dc.identifier.bibliographicCitation4th IEEE Electron Devices Technology and Manufacturing (EDTM) Conference 2020-
dc.citation.conferenceDate2020-03-16-
dc.citation.conferencePlaceMY-
dc.citation.title4th IEEE Electron Devices Technology and Manufacturing (EDTM) Conference 2020-
dc.contributor.affiliatedAuthorBAEK, ROCK HYUN-
dc.contributor.affiliatedAuthorYOON, JUN SIK-
dc.contributor.affiliatedAuthorJINSU, JEONG-
dc.contributor.affiliatedAuthorSEUNGHWAN, LEE-
dc.description.journalClass1-

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 BAEK, ROCK HYUN
Dept of Electrical Enginrg
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